1. Field of the Invention
The present invention relates to a technical field of a semiconductor integrated circuit device configured using a large number of MOS transistors, and particularly relates to a technical field of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) which is accessed through a signal path using a large number of MOS transistors.
2. Description of the Related Art
In recent years, as performance of a semiconductor integrated circuit device is improved, high speed operation and low voltage operation are required. Particularly, a semiconductor memory such as a DRAM has enabled high frequency operation, high speed access and low voltage operation due to finer manufacturing process, and higher performance is strongly required (e.g., see Japanese Patent Application Laid-open No. 2000-11649). Generally, complex operation needs to be performed when accessing the semiconductor memory, and delay time for the operation should be considered. In this case, if the delay time is constant for each of a large number of manufactured semiconductor memories, no problem arises. However, the delay time actually varies for each semiconductor memory due to process fluctuation. Such fluctuation of the delay time is further increased due to temperature fluctuation in addition to the process fluctuation. Then, delay difference when comparing a condition to maximize the delay time and a condition to minimize the delay time is increased, and this causes a problem of an increase in error of an access time for the semiconductor memory.
Meanwhile, as a measure against the operation delay, a method is known in which low threshold voltage transistors (low Vt transistors) having a threshold voltage (Vt) set lower than a standard value are used in a circuit contributing to the access time. By using such low Vt transistors, the delay time associated with the access time can be improved by about 10% relative to general transistors, and the fluctuation of the delay time can be slightly reduced.
However, variations of the low Vt transistor characteristics due to the process fluctuation causes various problems in the above conventional method. When the threshold voltage of the low Vt transistor varies downward, the operation delay is reduced, but both operation current and leak current are increased, thereby increasing consumption current. Meanwhile, when the threshold voltage of the low Vt transistor varies upward, the consumption current is reduced, but the operation delay is increased. In this case, if a power supply voltage of the low Vt transistors is lowered for the purpose of a reduction in the consumption current, the influence of the variation of the above threshold voltage is relatively increased, thereby further increasing the fluctuation of the delay time of the circuit. If the circuit is operated within a relatively wide temperature range, the influence of the variation of the low Vt transistor characteristics is remarkable due to both the process fluctuation and the temperature fluctuation. In this manner, it is a problem that in the conventional semiconductor integrated circuit device, it is difficult to reduce the fluctuation of the delay time in the circuit due to the process fluctuation and the temperature fluctuation without an increase in the consumption current, and the error of the access time or the like occurs.